The present invention relates to phase-locked loops, and more particular to a robust phase-lock detector for indicating when a phase-locked loop (PLL) is locked.
A phase-locked loop provides an output signal that has a desired phase relationship with a reference signal, although generally at a different frequency. The output signal frequency usually is some multiple of the frequency of the reference signal, i.e., fout=(N/m)fref or, if the PLL is fractional-N, fout=Nfref+(k/m)fref where N, m and k are integers. Typically the output signal is subdivided in frequency and the subdivided frequency signal is compared with the reference signal in a phase/frequency detector, producing an error signal indicative of the relative phase differential between the two signals—in this case fout=(N/m)fref as the most common type. The error signal is filtered by a loop filter and then used to control the phase/frequency of an oscillator to produce the output signal.
It is desirable to build phase-locked loops that have an indicator that tells a user or an electronic controller when phase lock is acquired, i.e., the reference and output signals have the desired phase relationship between them. A digital phase-locked loop is relatively cheap and easy to implement. The error signal is in the form of pulses or variations from a standard duty cycle. The absence of pulses or the presence of the standard duty cycle is used to indicate that the digital phase-locked loop is locked. Although the digital phase-locked loop is pretty good most of the time, it has poor noise performance which may produce spurious pulses or baseband anomalies. Therefore analog phase-locked loops are generally used where greater precision is required.
When a linear analog multiplier, such as a mixer or a Gilbert gain cell, is used as the phase detector in an analog phase-locked loop, typical lock detectors have problems being robust. Generally the error signal at the output of the detector is steered to zero volts d.c. by an integrating amplifier that follows the phase detector. A window detector monitors the d.c. voltage at the phase detector output and indicates when the phase deviates outside of a range specified for phase lock. The locked condition at the input of the window detector is zero volts d.c., plus or minus a small error voltage. The problem with the window detector is that other situations cause the phase detector output to be zero volts d.c. even when the phase-locked loop is not locked. For example when either or both of the signals are removed from the inputs of the phase detector, the output is zero volts d.c., but the phase-locked loop is not locked. This situation occurs when a part of the circuit is broken or either signal is powered “off.” In this case the window detector output indicates a “false” phase lock condition.
What is desired is a robust phase-lock detector for a phase-locked loop that minimizes false lock indications.